Wafer scale packaging scheme

ABSTRACT

A process and a package for achieving wafer scale packaging is described. A layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene is deposited on the surface of a chip. Via holes through this layer connect to the top surfaces of the studs that pass through the passivating layer of the chip. In one embodiment, the polymeric layer covers a redistribution network on a previously planarized surface of the chip. Individual chip-level networks are connected together in the kerf so that conductive posts may be formed inside the via holes through electroplating. After the formation of solder bumps, the wafer is diced into individual chips thereby isolating the individual redistribution networks. In a second embodiment, no redistribution network is present so electroless plating is used to form the posts. In a third embodiment, there is also no redistribution network but electroplating is made possible by using a contacting layer. Solder bumps attached to the posts are then formed by means of electroless plating, screen or stencil printing.

FIELD OF THE INVENTION

The invention relates to the general field of integrated circuitpackaging with particular reference to low cost methods for packagingindividual chips.

BACKGROUND OF THE INVENTION

Manufacturing techniques in use in the semiconductor industry havecontinued to improve in efficiency with resulting drops in cost. This isparticularly true for chip manufacturing where the cost per gatecontinues to drop year by year. Some of this advantage is, however,offset by the somewhat slower pace at which the cost of chip packaginghas been dropping. Until recently, chip manufacture and chip packaginghave been treated as essentially separate technologies and advances inthe former have not necessarily added value to the latter.

Recently, wafer scale packaging has been gaining in popularity. By thiswe mean that the entire wafer is packaged prior to its being separatedinto individual chips. A good example of this has been a recentpublication by M. Hou "Wafer level packaging for CSPs" in SemiconductorInternational, July 1998 pp. 305-308. CSPs (chip scale packages) firstmade their appearance around 1996. Since then there have been a numberof improvements exemplified by the structure described by Hou. In theprocess that she discusses, assembly of individual chip packages becomesan extension of the wafer fabrication line rather than a separateoperation dedicated to chip packaging.

Briefly, the process that is described by Hou involves compressionmolding of an encapsulant onto the top surface of the full wafer. Aspecial molding press, custom built to fit each type of wafer that is tobe used, is needed and reliance is made on the ability of the solderbumps, already present on the top surface of the completed wafer, topush through the plastic and reappear at the top surface of the package.Hou notes that this approach is suited primarily to low densitypackages.

SUMMARY OF THE INVENTION

It has been an object of the present invention to provide a package anda process for packaging semiconductor chips.

An additional object of the invention has been that said process resultin the simultaneous packaging of all chips on a single wafer at the sametime.

A still further object of the invention has been that said process notrequire any special jigs or fixtures for its implementation.

Yet another of object of the invention has been that said process besuitable for packages having a high density of interconnections.

One more object of the invention has been that said process providepackages that are significantly cheaper than those obtained throughindividual chip packaging processes.

These objects have been achieved by depositing a layer of a polymericmaterial, such as polyimide, silicone elastomer, or benzocyclobutene onthe surface of the chip. Via holes through this layer connect to the topsurfaces of the studs that pass through the passivating layer of thechip. In one embodiment, the polymeric layer covers a redistributionnetwork on a previously planarized surface of the chip. Individualchip-level networks are connected together in the kerf so thatconductive posts may be formed inside the via holes throughelectroplating. After the formation of solder bumps, the wafer is dicedinto individual chips thereby isolating the individual redistributionnetworks. In a second embodiment, no redistribution network is present.In a third embodiment, there is also no redistribution network butelectroplating is made possible by using a contacting layer. Thepolymeric layer then also serves as the final planarizing layer.Conductive posts are then formed in the via holes by means ofelectroless plating.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a schematic cross-section of a fully packaged integratedcircuit including a top layer of polymeric material that communicates tothe chip level through extended via holes and a redistribution network.

FIG. 1b is a schematic cross-section of a fully packaged integratedcircuit including a top layer of polymeric material that communicatesdirectly to the chip level through extended via holes.

FIG. 2 shows parts of an integrated circuit prior to packaging.

FIG. 3 shows the structure of FIG. 2 after the addition of a planarizinglayer that includes an access hole to the studs as well as a contactinglayer.

FIG. 4 shows the structure of FIG. 3 following the addition of aredistribution layer.

FIG. 5 shows structure of FIG. 4 following the addition of a layer ofpolymetric material in which a via hole has been formed.

FIG. 6 is the structure seen in FIG. 5 after the via hole has beenoverfilled with metal to form a conducting post.

FIG. 7a shows the structure of FIG. 6 following the formation of asolder ball at the end of a projecting post together with etchback toform a `lollipop` structure.

FIG. 7b is like FIG. 7a except that a layer of UBM has been insertedbetween the solder ball and the polymeric layer.

FIG. 8 shows the structure of FIG. 2 following the addition of a layerof polymetric material in which a via hole has been formed directlyabove the stud.

FIG. 9 is the structure seen in FIG. 8 after the via hole has beenoverfilled with metal to form a conducting post.

FIG. 10a shows the structure of FIG. 9 following the formation of asolder ball at the end of a projecting post.

FIG. 10b is like FIG. 10a except that a layer of UBM has been insertedbetween the solder ball and the polymeric layer.

FIGS. 11a and 11b illustrate how the shape of a via hole formed in aphotosensitive material may be modified depending on its properties andon the exposure mode used.

FIG. 12 shows how individual redistribution networks on chips may beconnected together in the kerf to form a single common distributionnetwork.

FIG. 13 shows a freestanding post which is to be almost covered by alayer of polymeric material.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention teaches a process and a package for encapsulatingan entire wafer with a layer of a polymeric material which is applied byany of several conventional techniques such as spin coating, dipping,spraying, or as a dry film and describes several low-cost ways ofestablishing electrical communication between terminals at the surfaceof the chip and solder bumps on the outer surface of the package. Wewill describe two embodiments of the invention. In the first of theseembodiments electroplating is used to form parts of the package but itshould be understood that electroless plating may be substituted forselected subprocesses without departing from the spirit of theinvention.

In FIG. 1a we show a schematic representation of one embodiment. Anintegrated circuit is shown in cross-section as a series of layers thathave been formed over silicon substrate 1. Successive layers 2, 3, and 4represent the device level and two levels of wiring respectively. Eachlayer has been planarized. The top-level wiring, including I/O pads suchas 6 and 7 has been formed on the top surface of layer 4 and thencovered by passivating layer 13 (usually silicon nitride) which in turnhas been covered by a final planarizing layer 5 (typically, but notnecessarily, of polyimide). In general, the pattern of studs 8 will notcoincide with the pattern of solder terminals on the card or board towhich the chip is to be attached. It is also possible that more than onepattern of the ball grid array (BGA) on the outer surface of the packageis needed, depending on where this particular chip is to be attached. Inorder to deal with this, it is standard to use a redistribution network,normally located on the top surface of planarizing layer 5. A part ofthe redistribution network is exemplified by layer 14. An additionalfeature of packages of this type (not shown in FIG. 1a but illustratedin later figures) is a contacting layer at the interface between layers5 and 10.

Using conventional manufacturing techniques, the chip manufacturingprocess for a standard flip chip would normally terminate at this point.In the wafer scale packaging approach, the process is continued with theapplication of a plastic (polymeric) layer 10 that gives the chip bothenvironmental as well as mechanical protection. In order to be able tomake electrical contact to layer 14, via holes 11, filled with asuitable conductive material, need to be formed and fresh solder bumps12 attached to their top ends.

FIG. 1b is a schematic view of a second embodiment, representing a lowercost version of the package. It differs from FIG. 1a in that noredistribution network is present. This implies that the pattern ofconnecting studs is the same as the pattern of solder terminals on thenext level package. This simplification allows final planarization layer5 (in FIG. 1a) to be omitted from the structure. Instead, polymericlayer 15 is allowed to extend all the way down to passivating layer 13.

We have identified three types of polymeric material that are suitablefor wafer scale packaging of the type disclosed in the presentinvention. These are polyimides, silicone elastomers, andbenzocyclobutene (BCB). All three types are readily applied by spincoating while in their uncured form and they may then be hardened(cured) through reaction with a hardening agent, usually, but notnecessarily, accelerated by heating. Additionally, the polyimides areavailable in the form of dry films which can be applied directly to asurface by means of an adhesive. The choice of which material to usedepends on a number of factors. These include:

Temperature coefficient of expansion (TCE)--should be low so as to matchthat of the metal studs, thereby minimizing local stresses at thestud-polymer interface

Young's modulus (degree of inelasticity) Y--should be low to reducetransmission of stress to the posts and to decouple the thermal mismatchbetween silicon and plastic

Water absorption--should be low to ensure stability

Moisture permeability--should be low to protect the semiconductor

Adhesion--should be high

Electrical properties, such as dielectric constant, dielectric loss,resistivity, etc. tend to be adequate for all three of these materials.

It is thus apparent that selection of the correct polymeric materialwill depend on a number of factors such as layer thickness, anticipatedtemperature range during life, atmosphere to which package will beexposed, BGA density, chip size, I/O count, etc. Additionally, as notedbelow, use of the photosensitive versions of these materials offerseveral advantages, including the ability to tailor the shape of the viaholes, so when such versions are readily available commercially (as inthe case of polyimides and BCB) this must also be considered.

In TABLE I below we summarize some of the properties of these materials.

The numbers given represent averages for the class of materials

                  TABLE I                                                         ______________________________________                                        PROPERTY  POLYIMIDES ELASTOMERS  BCB                                          ______________________________________                                        Cure temperature                                                                        350° C.                                                                           room temperature                                                                          250° C.                                 Young's modulus 3.4 Gpa very small 2 GPa                                      Water absorption 3% low 0.2%                                                  TCE 40 × 10.sup.-6 /° C. 1 × 10.sup.-6 /° C.                                       52 × 10.sup.-6 /° C.                                              Adhesion fair to good Good - excellent                                       Fair to good                                 ______________________________________                                    

Even if the polymeric layer is able to absorb stress inherent to thedesign without, for example, cracking, it is also necessary for themetal posts that fill the via holes to exhibit good elastic behavior sothat, if need be, they can bend rather than break. It can be shown thata metal post of length L, fixed at one end and free at the other,requires a force F to displace it by an amount d at the free end. Themagnitude of F is calculated according to the equation:

    F=(3Yld)/L.sup.3, where Y=Young's modulus and I=moment of inertia

Thus, to minimize the force required to cause a given displacement (i.e.for the post to be flexible), both Y and I need to be minimized. As faras Y is concerned, gold and solder are good choices although copper isto be preferred for other reasons, while I is proportional to the massof the post, implying that a small diameter and low density are best.

We will now describe the three embodiments of the invention. Althoughthese embodiments differ in their total approach they both share thefollowing initial steps:

Referring now to FIG. 2, all embodiments begin with the provision of asemiconductor wafer in which multiple chips have been formed. Each suchchip has an image on the surface of the wafer and each such chip imageis separated from all others by a region known as the kerf because itwill be used later by the saw blade for dicing the wafer into individualchips. Integrated circuit 21 is shown as having been formed over siliconsubstrate 20. Layer 22 represents a passivating layer similar to layer13 in FIGS. 1a and 1b, while connecting pad 23 (corresponding to stud 7in FIG. 1a) is seen as being open to the outside world.

FIRST EMBODIMENT

In FIG. 3, layer 30 represents everything in FIG. 2 below the pad 23,including layer 22. Layer 31 of polyimide has been deposited by spincoating onto the surface of 30 and opening 32 has been formed in itusing standard photolithographic techniques, including photosensitivepolyimides. Layer 31 is generally between about 3 and 20 microns thick.This is followed by the deposition of layer 33 of chrome-coppergenerally but not necessarily, by sputtering, to a thickness that isbetween about 500 and 2,000 Angstroms.

With layer 33 (in FIG. 3) covering the entire surface of the wafer,photoresist is laid down and patterned so that the surface is coveredeverywhere except where it is intended to have the redistributionnetwork. In an important feature of the invention, the individualchip-level distribution networks are connected to one another by usingthe otherwise empty space provided by the kerf, thereby forming a commondistribution network as illustrated in FIG. 12 where individualredistribution networks in chip images 93-96 are seen to be connectedtogether in the kerf regions 98 thereby forming a common distributionnetwork one end of which is designated as 99.

Electroplating is then used to build up the thickness of the metal thatforms the common distribution network. Electrical contact is made tometal layer 33 allowing metal to be plated in all areas not covered bythe photoresist. For this metal we have preferred to use copper althoughmetals such as aluminum could also have been used together withnon-electroplating methods. At the completion of electroplating,resulting in an additional thickness of metal between about 0.5 and 5microns thick, the photoresist is removed. An example of part of theredistribution network is shown as layer 41 in FIG. 4 and all parts ofthe contacting layer not covered by the redistribution network areselectively removed.

Next, a layer of polymeric material is laid down. This is shown as layer51 in FIG. 5. Its thickness is between about 20 and 250 microns. Viahole 52 is then formed in it. This corresponds to via holes 11 in FIG.1a. Several different subprocesses were available for the formation ofthis via hole:

(a) the polymeric material is photosensitive. In the case of BCB and thepolyimides, there are many commercial compositions available for this.Via holes 52 are then formed by exposing through a suitable mask anddeveloping. By controlling the type of photosensitive materials as wellas the exposure conditions, the shape of the via holes can becontrolled. For example, if the photosensitive material generates anegative image of the mask this can cause the via holes to be widerclosest to their bottom, i.e. closest to layer 41 as illustrated in FIG.11a. On the other hand, if the photosensitive material generates apositive image of the mask and if an imaging system with a low depth offocus is used and if the image is focused in a plane midway between thetwo surfaces, the effect is for the via holes to be narrowest at a pointhalfway down the holes, as illustrated in FIG. 11b. In general, theresulting conductive posts will have better strength and adhesion thanconventional (simple cylindrical) posts.

(b) the polymeric material is etched in the usual way using aphotoresist mask. Since the photoresist and the polymeric materialrespond somewhat similarly to the etchants usually used for the latter,a hard mask (e.g. CVD silicon oxide) is often used.

(c) the polymeric material is etched using laser drilling. For polymericlayers thicker than about 100 microns this is the preferred method. Anexample of a laser well suited to this application is an eximer (209 nm)laser or a CO₂ (10.6 microns) laser with the capability of forming holeswith diameters as low as about 50 microns.

Then, using a second electroplating step (contact to layer 41 being madethrough the common distribution network), additional metal (preferablycopper but other metals such as gold, solder (such as lead-tin), oraluminum (non-electroplated), could also have been used) was plated ontoall exposed surfaces of layer 41. In other words, via hole 52 was filledwith metal, with post formation being continued past the point at whichit was just filled. Thus the appearance of the structure following theoverfilling of via hole 52 approximated that shown schematically in FIG.6 where stud 67 is seen to have a rounded top projecting above thesurface of layer 51. This projection of the post above the polymericmaterial surface is needed to anchor the solder bumps which are grown inthe next step of the process. This `anchor` effect can be furtherenhanced by etching back the polyimide material to some extent, asillustrated in FIG. 7a, to generate a `lollipop` structure for thepost-bump combination.

Referring now to FIG. 7a, a solder bump such as 71 is grown over theprojecting tip of 67. Since electrical contact can still be made to 67through the common distribution network, electroplating is the preferredmethod for accomplishing this. In general, electroplating offers bettercontrol, in particular control of the composition of the depositedlayer, than is achievable by, for example, electroless plating.

As a variation to this embodiment, the extensions of the posts may befirst coated with a UBM layer 72 as shown in FIG. 7b prior to growingsolder bump 71. This is done in the usual manner by first depositingover the entire surface and then patterning and etching. The advantageof providing this extra layer of UBM is that the base contact area forthe solder balls is enlarged and hence their adhesion is increased. Itwould be used in cases where large solder balls are required. In bothcases, the diameter of the solder bumps was between about 100 and 300microns with a pitch that was typically between about 200 and 800microns.

Once solder bumps 71 have been formed, the wafer is diced intoindividual chips by cutting along the kerf. In so doing the commondistribution network is destroyed but each chip retains its ownindividual redistribution network.

SECOND EMBODIMENT

Unlike the first embodiment, there is no redistribution network presenton the surface of the unpackaged chips. Therefore, the process proceedsdirectly from the structure of FIG. 2 to the step of laying down a layerof polymeric material 80 (as illustrated in FIG. 8) whose thickness isbetween about 20 and 250 microns. As in the first embodiment, via holes82 are formed in it with the added constraint that they are locateddirectly above studs 23. These correspond to the via holes that willcontain conductive posts 11 in FIG. 1b. In order to form these viaholes, one of three subprocesses were used:

(a) the polymeric material is photosensitive. In the case of polyimidesor BCB, there are many commercial compositions available for this. Viaholes 52 are then formed by exposing through a suitable mask anddeveloping. By controlling the type of photosensitive material as wellas the exposure conditions, the shape of the via holes can becontrolled. For example, if the photosensitive material generates anegative image of the mask this can cause the via holes to be widerclosest to their bottom, i.e. closest to layer 41 as illustrated in FIG.11a. On the other hand, if the photosensitive material generates apositive image of the mask and if an imaging system with a low depth offocus is used and if the image is focused in a plane midway between thetwo surfaces, the effect is for the via holes to be narrowest at a pointhalfway down the holes as illustrated in FIG. 11b.

(b) the polymeric material is etched in the usual way using aphotoresist mask. Since the photoresist and the polymeric materialrespond somewhat similarly to the etchants usually used for the latter,a hard mask (e.g. CVD silicon oxide) is often used .

(c) the polymeric material is etched using laser drilling. For polymericlayers thicker than about 100 microns this is the preferred method. Anexample of a laser well suited to this application is an eximer (209 nm)laser or a CO₂ (10.6 microns) laser with the capability of forming holeswith diameters as low as about 50 microns.

Then, using electroless plating, (electrical contact to I/O pads such as6 or 7 not being available in this embodiment), additional metal(preferably copper but other metals such as gold, solder, or nickelcould also have been used) was plated onto all exposed surfaces of studs23. In other words, via hole 82 was filled with metal.

The filling of 82 was continued past the point at which it was justfilled. Thus the appearance of the structure following the overfillingof via hole 82 approximated that shown schematically in FIG. 9 wherepost 87 is seen to have a rounded top projecting above the surface oflayer 80. As in the first embodiment, this projection of the post abovethe polymeric material surface is needed to anchor the solder bumpswhich are grown in the next step of the process.

Referring now to FIG. 10a, a solder bump 81 is grown over the projectingtip of 87. Since electrical contact cannot be made to 87, electrolessplating has to be used.

As a variation to this embodiment, the extensions of the posts may befirst coated with a UBM layer 88 (as shown in FIG. 10b) prior to growingsolder bump 81. This is done in the usual manner by first depositingover the entire surface and then patterning and etching. The advantageof providing this extra layer of UBM is that the base contact area forthe solder balls is enlarged and hence their adhesion is increased. Itwould be used in cases where large solder balls are required. In bothcases, the diameter of the solder bumps was between about 100 and 300microns with a pitch that was typically between about 200 and 800microns.

As an alternative, low cost, variation, instead of forming the solderbumps through plating, they may be laid down by means of screen printingor stenciling. This is a viable approach for solder bumps havingdiameters in excess of about 100 microns with a pitch that is greaterthan about 200 microns.

Once solder bumps 81 have been formed, the wafer is diced intoindividual chips by cutting along the kerf.

THIRD EMBODIMENT

As in the second embodiment, there is no redistribution network presenton the surface of the unpackaged chips. However, unlike the secondembodiment, the preferred metal deposition method is electroplating.Accordingly, a contacting metal layer is deposited over the entirepassivation layer. See layer 45 in FIG. 13. This is followed by coatingwith a layer a photoresist in which via holes are formed in a similarmanner to the formation of via holes in the photosensitive versions ofthe polymers as described in the first and second embodiments, includingtechniques for controlling the shapes of these via holes. The via holesare then filled with metal by means of electroplating following whichthe photoresist is stripped, leaving behind freestanding metal postssuch as 46 in FIG. 13.

Then, using a differential etch, the contacting layer is removed withoutany attack on the freestanding posts. Next, the polymeric material isapplied to the wafer as a single layer whose thickness is less than theheight of the freestanding posts, thereby allowing a certain amount ofuncovered post material to project above the surface of the polymer. Thestructure is then completed as in the second embodiment through theformation of solder bumps by electroless plating, screen printing, orstenciling.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

What is claimed is:
 1. A process for wafer scale packaging,comprising:providing a semiconductor wafer, including chip imagesseparated by a kerf area and having a topmost passivating layer throughwhich pass connecting studs; forming a polymeric body having a pluralityof metal costs in contact with, and fixed to, said connecting studs andpassing vertically through said polymeric body from said studs; andwherein said posts are of a diameter and height and of a material thatthey can bend to absorb stress due to thermal mismatch between saidsemiconductor wafer and said polymeric body.
 2. The process of claim 1wherein said polymeric body is a polyimide or a silicone elastomer orbenzocyclobutene.
 3. The process of claim 1 further, comprising formingvia holes in said polymeric body and then forming the conducting postsinside the via holes.
 4. The process of claim 3 wherein said via holesare formed by chemical etching or by laser drilling.
 5. The process ofclaim 3 wherein said metal posts of formed by electroplating or byelectroless plating.
 6. The process of claim 1 wherein a bending forceexerted at a free end of a metal post of length L displaced by an amountd, is according to a formula F=(3Yld)/L³, where Y=Young's modulus andI=moment of inertia.
 7. The process of claim 1 wherein said polymericbody is laid down by spin coating or by dipping or by spraying or in theform of a dry film with an adhesive undercoating.
 8. A process for waferscale packaging, comprising the sequential steps of:(a) providing asemiconductor wafer, including chip images separated by a kerf area andhaving a topmost passivating layer through which pass connecting studs;(b) depositing a planarizing layer of polyimide over the passivatinglayer and then patterning and etching said polyimide layer to formopenings over the connecting studs; (c) depositing a UBM layer on saidpolyimide layer, depositing a first layer of photoresist on the UBMlayer, and then patterning the photoresist to leave uncovered areas ofthe UBM layer that define a common distribution network comprisingchip-level redistribution networks connected to each other in the kerf;(d) by means of electroplating, depositing a first layer of metal on allareas of the UBM layer not covered by photoresist; (e) removing thefirst layer of photoresist and selectively removing all parts of the UBMlayer that are not covered by said first layer of metal; (f) laying downa layer of polymeric material and forming therein via holes that extenddown to the level of the common distribution network; (g) by means ofelectroplating, depositing a second layer of metal on all metallic areasnot covered by the second layer of polymeric material until the viaholes have been overfilled with said second metal layer, thereby formingposts with projections that extend by an amount above the layer ofpolymeric material; (h) by means of electroplating, forming solder bumpscentered around and attached to, said post projections; and (i) slicingthe wafer into individual chips, thereby cutting all lines in the kerfarea and electrically dividing said common distribution network intochip-level redistribution networks.
 9. The process of claim 8 whereinsaid polymeric body is a polyimide or a silicone elastomer orbenzocyclobutene.
 10. The process of claim 8 wherein said polymeric bodyis a layer having a thickness of between about 20 and 250 microns. 11.The process of claim 8 wherein the step of forming via holes in thelayer of polymeric material further comprises using a photo sensitiveversion of the polyimeric material which is exposed through a mask andthen developed to form the holes.
 12. The process claim 8 wherein thestep of forming via holes in the layer of polymeric material furthercomprises using a photoresist mask in conjunction with a hard mask overthe polymeric material and then etching the polymeric material.
 13. Theprocess of claim 8 wherein the step of forming via holes in the layer ofpolymeric material further comprises using laser drilling.
 14. Theprocess of claim 8 wherein said second metal layer has a thicknessbetween about 20 and 250 microns and is selected from the group ofconsisting of copper, gold, solder, and aluminum.
 15. The process ofclaim 11 wherein said photosensitive version provides a negative imageof the mask which causes the via holes to be wider closest to the secondlayer of metal.
 16. The process of claim 11 further comprising:using aphotosensitive version of the polymeric material that provides apositive image of the mask and that has upper and lower surfaces;employing an imaging system that has a low depth of focus; and focusingin a plane midway between said surfaces, thereby causing said via holesto be narrowest at a point halfway down the holes.
 17. The process ofclaim 8 further comprising etching back the layer of polymeric materialto generate a lollipop structure from the post and solder bumpcombination.
 18. The process of claim 8 further comprising coating theuncovered portions of the posts with a UBM layer before forming thesolder bumps.
 19. A process for wafer scale packaging, comprising thesequential steps of:(a) providing a semiconductor wafer containingintegrated circuits, including a topmost passivating layer through whichpass conductive studs that connect to points within said integratedcircuits; (b) laying down a layer of polymeric material and formingtherein via holes that overlie and extend down to said conductive studs;(c) by means of electroless plating, depositing a layer of metal on allmetallic areas not covered by polymeric material until the via holeshave been overfilled with said metal layer thereby forming posts withprojections that extend above the layer of polymeric material by anamount; (d) by means of electroless plating, forming solder bumpscentered around and attached to, said post projections; and (e) slicingthe wafer into individual chips.
 20. The process of claim 19 whereinsaid polymeric body is a polyimide or a silicone elastomer orbenzocyclobutene.
 21. The process of claim 19 wherein said polyimericbody is a layer having a thickness of between about 20 and 250 microns.22. The process of claim 19 wherein the step of forming via holes in thelayer of polymeric material further comprises using a photosensitiveversion of the polymeric material which is exposed through a mask andthen developed to form the holes.
 23. The process of claim 19 whereinthe step of forming via holes in the layer of polymeric material furthercomprises using a photoresist mask, together with a hard mask, over thepolymeric material and then etching the polymeric material.
 24. Theprocess of claim 19 wherein the step of forming via holes in the layerof polymeric material further comprises using laser drilling.
 25. Theprocess of claim 22 wherein photosensitive version provides a negativeimage of the mask which causes the via holes to be wider closest to thesecond layer of metal.
 26. The process of claim 22 furthercomprising:using a photosensitive version of the polymeric material thatprovides a positive image of the mask and that as upper and lowersurfaces; employing an imaging system that has a low depth of focus; andfocusing in a plane midway between said surfaces, thereby causing saidvia holes to be narrowest at a point halfway down the holes.
 27. Theprocess of claim 19 wherein the amount that the posts project above thelayer of polyimeric material is between about 10 and 75 microns.
 28. Theprocess of claim 19 further comprising coating the uncovered portions ofthe posts with a UBM layer before forming the solder bumps.
 29. Theprocess of claim 19 wherein, in step (d) instead of electroless plating,the solder bumps are laid down using screen printing stenciling.
 30. Aprocess for wafer scale packaging, comprising the sequential stepsof:(a) providing a semiconductor wafer containing an integrated circuit,including a topmost passivating layer through which pass conductivestuds that connect to points within said integrated circuits; (b)depositing a contacting layer of metal over the passivating layer; (c)laying down a layer of photoresist and forming therein via holes thatextend down to the contacting metal layer; (d) by means ofelectroplating, depositing a layer of metal on all contacting metalareas not covered by photoresist until the via holes have been filledwith said metal layer; (e) removing the layer of photoresist, therebyforming freestanding metal posts; (f) without attacking said posts,removing the contacting metal layer; (g) spreading over the entire wafera layer of polymeric material whereby part of the posts remainuncovered; (h) forming solder bumps centered around and attached to,said post projections; and (i) slicing the wafer into individual chips.